High power RF transistors such as LDMOS (laterally diffused metal oxide semiconductor) transistors have input and output impedances significantly lower than 50 ohms (high Q impedance), yet the functioning RF circuit has to be matched to 50 ohms. To facilitate the impedance match to 50 ohms, the RF transistor is typically designed with a match circuit on the input and output of the transistor that is integrated into the packaged transistor. The match network helps reduce the Q of the packaged transistor, making it easier to match to 50 ohms. Typically the improvement in impedance can only be achieved in a narrow frequency range. In addition, the match network helps to shape the frequency response of the transistor and amplifier such that there is high gain at the desired operating frequency, and the gain is suppressed outside that frequency range. Typically the gain at low frequencies is not adequately suppressed, and there can be a high forward voltage gain bump at low frequencies that leads to instability, ruggedness and linearity correction problems for the amplifier. Apart from the gain response of the transistor, the maximum available gain (Gmax) of the amplifier at low frequencies can also lead to stability, ruggedness and correction problems when not properly suppressed. This is particularly problematic for RF transistor applications where the signal input to the transistor is a complex modulation of several high frequency tones (e.g. 2.0 GHz and 2.1 GHz tones), the mixing of which results in signals at low frequencies (e.g. 100 MHz in this example) which are amplified by the low frequency forward voltage gain bump.
In one conventional implementation, the RF transistor is matched on the input with a low-pass L-C-L network. This network matches the input impedance of the transistor to a lower Q over a specific frequency range. However, the low-pass network does not suppress the low frequency response of the transistor and hence the maximum available gain remains high at low frequencies leading to stability, ruggedness and linearity correction problems. The gain response of the transistor also shows a high forward voltage gain bump at low frequency.
In another conventional implementation, the transistor input is matched with a low-pass L-C-L network and the output is matched with a high-pass shunt L network terminating on a blocking capacitor which has a low-frequency bypass capacitor connected in parallel through an L-R network. The low-frequency bypass capacitor reduces the forward voltage gain bump at low frequencies for the case where the source and load are matched to 50 ohms. However, this implementation does not suppress the maximum available gain at low frequencies, hence when the source and/or load is mismatched from 50 ohms high gain at low frequencies results which leads to stability, ruggedness and linearity correction problems.